This invention relates to a method for obtaining a multi-level ROM in an EEPROM process flow, as well as a memory cell structure formed thereby.
The invention relates to a ROM structure having transistor cells which are integrated in a semiconductor by a dual gate EEPROM process flow, along with transistors for electrically erasable non-volatile memory cells, and with storage circuitry transistors; all these transistors having active areas covered with a layer of gate oxide, itself overlaid with a polysilicon layer.
In this technical field, there is a pressing demand for integration of both ROM (Read Only Memory) circuits and electrically erasable non-volatile memories, such as EEPROMs and/or Flash EEPROMs, into a single semiconductor electronic device. This demand comes especially from the smart card market, and involves considerable complications to the process of manufacturing such integrated electronic devices.
The technologies employed in the manufacture of either types of circuits are not fully compatible, resulting in increased manufacturing costs and less-easily-achieved high throughputs. Furthermore, advancements in cryptography require extending codes in terms of number of bits which are difficult to decode by reverse engineering.
Also known is that a set or array of ROM cells essentially consists of an array of MOS transistors having conventional source, drain and gate terminals, and having their threshold voltages set during the manufacturing process.
These thresholds are differentiated such that, through the intermediary of an appropriate sensing circuit, it becomes possible to determine which of the cells are ON (logic 1) and which are OFF (logic 0) for a given bias of the transistor gate terminals. Those cells which are in a logic 1 state usually can be discriminated from those in a logic 0 state by implanting the source region and not implanting drain junctions during the step of implanting these transistor regions.
This prior approach provides cells with a logic 1 and/or a logic 0 value, but disallows discriminating them immediately by optical scanning.
There have been other approaches whereby the logic 1 and 0 values can be discriminated based on the presence or the absence of a transistor. However, there is no currently available technology which can provide a multi-level ROM structure, i.e. one capable of storing plural logic values in each memory cell.
Embodiments of this invention provide a novel method for obtaining a multi-level ROM in a dual gate CMOS process, such that a higher capacity for data storage can be provided by a readily integrated product with CMOS technology.
Principles of the invention provide a ROM cell which can store six distinct logic levels. This cell is formed by first utilizing the LV and HV well implantations and the capacitor implantation to provide additional levels in the ROM, whereafter two different dopant implantings are used for the polysilicon layer which forms the transistor gate region.
Briefly, the step of implanting the source/drain regions of the transistor which comprises a cell is carried out separately from the polysilicon implanting step.
Therefore, presented is a method for obtaining a multi-level ROM in a dual gate EEPROM process flow. The method begins by defining active areas on a semiconductor substrate respectively for: transistors of ROM cells, transistors of electrically erasable non-volatile memory cells, and additional transistors of the storage circuitry. Then integrated capacitors in the storage circuit are implanted, and during this implantation, at least an active area of the ROM cell is subjected to the same implantation.
In another embodiment, when the polysilicon layer is being etched to define the gate regions of the ROM cells, the gate regions of the high-voltage transistors are also defined.